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tny375-380 tinyswitch-pk family www.powerint.com september 2012 energy-effcient, off-line switcher with enhanced peak power performance ? obsolete product C not recommended for new designs pi-4266-012009 d ac in dc out + t inyswitch-pk d s en/uv bp/m output power table product 3 230 vac 15% 85-265 vac adapter 1 open frame 2 peak adapter 1 open frame 2 peak TNY375P/g/d 4 8.5 w 15 w 16.5 w 6 w 11.5 w 12.5 w tny376p/g/d 4 10 w 19 w 22 w 7 w 15 w 17 w tny377p/g 13 w 23.5 w 28 w 8 w 18 w 23 w tny378p/g 16 w 28 w 34 w 10 w 21.5 w 27 w tny379p/g 18 w 32 w 39 w 12 w 25 w 31 w tny380p/g 20 w 36.5 w 45 w 14 w 28.5 w 35 w table 1. output power table. notes: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 c ambient. use of an external heat sink will increase power capability. 2. minimum continuous power in an open frame design (see key applications considerations). 3. packages: p: dip-8c, g: smd-8c, d: so-8c. lead free only. see part ordering information. 4. see key application considerations. product highlights lowest system cost with enhanced flexibility ? simple on/off control, no loop compensation needed ? unique peak mode feature extends power range without increasing transformer size ? maximum frequency and current limit boosted at peak loads ? selectable current limit through bp/m capacitor value ? higher current limit extends maximum power in open frame ? lower current limit improves effciency in enclosed adapters ? allows optimum tinyswitch-pk choice by swapping devices with no other circuit redesign ? tight i 2 f parameter tolerance reduces system cost ? maximizes mosfet and magnetics power delivery ? on time extension C typically extends low line regulation range/ hold-up time to reduce input bulk capacitance ? self-biased: no bias winding required for tny375-376; winding required for tny377-380 ? frequency jittering reduces emi flter costs ? optimized pin out eases pcb/external heat sinking ? quiet source-connected heat sink pins for low emi enhanced safety and reliability features ? accurate hysteretic thermal shutdown with automatic recovery provides complete system level overload protection and eliminates need for manual reset ? auto-restart delivers <3% maximum power in short circuit and open loop fault conditions ? output overvoltage shutdown with optional zener ? line undervoltage detect threshold set using a single resistor ? very low component count enhances reliability and enables single sided printed circuit board layout ? high bandwidth provides fast turn on with no overshoot and excellent transient load response ? extended creepage between drain and all other pins improves feld reliability ecosmart ? C extremely energy effcient ? easily meets all global energy effciency regulations ? no-load <170 mw at 265 vac without bias winding, <60 mw with bias winding ? on/off control provides constant effciency down to very light loads C ideal for mandatory cec effciency regulations and 1 w pc standby requirements applications ? applications with high peak-to-continuous power demands C dvds, pvrs, active speakers (e.g. pc audio), audio amplifers, modems, photo printers ? applications with high power demands at startup (large output capacitance or motor loads) C pc standby, low voltage motor drives description tinyswitch-pk incorporates a 700 v mosfet, oscillator, high- voltage switched current source, current limit (user selectable), and thermal shutdown circuitry. a unique peak mode feature boosts current limit and frequency for peak load conditions. the boosted current limit provides the peak output power while the increased peak mode frequency ensures the transformer can be sized for continuous load conditions rather than peak power demands. figure 1. typical peak power application.
rev. c 09/12 2 tny375-380 www.powerint.com pin functional description drain (d) pin: this pin is the power mosfet drain connection. it provides internal operating current for both start-up and steady-state operation. bypass/multi-function (bp/m) pin: this pin has multiple functions: 1. it is the connection point for an external bypass capacitor for the internally generated 5.85 v supply. 2. it is a mode selector for the current limit value, depending on the value of the capacitance added. use of a 0.1 mf capacitor results in the standard current limit value. use of a 1 m f capacitor results in the current limit being reduced to that of the next smaller device size. use of a 10 mf capacitor results in the current limit being increased to that of the next larger device. 3. it provides a shutdown function. when the current into the bypass pin exceeds 7 ma, the device latches off until the bp/m voltage drops below 4.9 v, during a power down or when a line undervoltage is detected. this can be used to provide an output overvoltage function with a zener diode connected from the bp/m pin to a bias winding supply. enable/undervoltage (en/uv) pin: this pin has dual functions: enable input and line undervoltage sense. during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is terminated when a current greater than a threshold current is drawn from this pin. switching resumes when the current being pi-4550-121406 clock oscilla t or 5.85 v 4.9 v source (s) s r q dc max byp ass/ mul ti-function (bp/m) + - v i limit fa ul t present current limit comp ara to r enable leading edge blanking thermal shutdown + - drain (d) regula t or 5.85 v byp ass pin under-vol ta ge 1.0 v + v t enable/ under- volta ge (en/uv) q 1 15 a 25 a line under-vol ta ge reset aut o- rest art counter jitter 2x 1.0 v 6.4 v byp ass cap acit or select and current limit st a te machine ovp la tch reset figure 2 functional block diagram. pi-4348-042809 d s bp/m s s en/uv p package (dip-8c) g package (smd-8c) d package (so-8c) 8 5 7 1 4 2 s 6 figure 3. pin confguration.
rev. c 09/12 3 tny375-380 www.powerint.com pulled from the pin drops to less than a threshold current. a modulation of the threshold current reduces group pulsing. the threshold current is between 75 m a and 115 m a. the en/uv pin also senses line undervoltage conditions through an external resistor connected to the dc line voltage. if there is no external resistor connected to this pin, tinyswitch-pk detects its absence and disables the line under- voltage function. source (s) pin: this pin is internally connected to the output mosfet source for high voltage power return and control circuit common. tinyswitch-pk functional description tinyswitch-pk combines a high voltage power mosfet switch with a power supply controller in one device. unlike conventional pwm (pulse width modulator) controllers, it uses a simple on/ off control to regulate the output voltage. the controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.85 v regulator, bypass/ multi-function pin undervoltage, overvoltage circuit, and current limit selection circuitry, over-temperature protection, current limit circuit, leading edge blanking, and a 700 v power mosfet. tinyswitch-pk incorporates additional circuitry for line undervoltage sense, auto-restart, adaptive switching cycle on-time extension, and frequency jitter. figure 2 shows the functional block diagram with the most important features. oscillator the typical oscillator frequency is internally set to an average of 264 khz (at the highest current limit level). two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of each cycle. the oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 3% of the oscillator frequency, to minimize emi emission. the modulation rate of the frequency jitter is set to 1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 4 illustrates the frequency jitter with an oscillator frequency of 264 khz. enable input and current limit state machine the enable input circuit at the en/uv pin consists of a low impedance source follower output set at 1.2 v. the current through the source follower is limited to 115 m a. when the current out of this pin exceeds the threshold current, a low logic level (disable) is generated at the output of the enable circuit until the current out of this pin is reduced to less than the threshold current. this enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled). if low, the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the en/uv pin voltage or current during the remainder of the cycle are ignored. when a cycle is disabled, the en/uv pin is sampled at 264 khz. this faster sampling enables the power supply to respond faster without being required to wait for completion of the full period. the current limit state machine reduces the current limit by discrete amounts at light loads when tinyswitch-pk is likely to switch in the audible frequency range. the lower current limit raises the effective switching frequency above the audio range and reduces the transformer fux density, including the associated audible noise. the state machine monitors the sequence of enable events to determine the load condition and adjusts the current limit level accordingly in discrete amounts. under most operating conditions (except when close to no-load), the low impedance of the source follower keeps the voltage on the en/uv pin from going much below 1.2 v in the disabled state. this improves the response time of the optocoupler that is usually connected to this pin. 5.85 v regulator and 6.4 v shunt voltage clamp the 5.85 v regulator charges the bypass capacitor connected to the bypass pin to 5.85 v by drawing a current from the voltage on the drain pin whenever the mosfet is off. the bypass/multi-function pin is the internal supply voltage node. when the mosfet is on, the device operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows the tny375 and tny376 to operate continuously from current taken from the drain pin. a bypass capacitor value of 0.1 m f is suffcient for both high frequency decoupling and energy storage. in addition, there is a 6.4 v shunt regulator clamping the bypass/multi-function pin at 6.4 v when current is provided to the bypass/multi-function pin through an external resistor. this facilitates powering of tinyswitch-pk externally through a bias winding as required for tny377-380. powering the tinyswitch-pk externally in this way also decreases the no-load consumption to below 60 mw. 600 0 2.5 5 280 khz 248 khz v drain ti me (s) pi-4539-102207 500 400 300 200 100 0 figure 4. frequency jitter.
rev. c 09/12 4 tny375-380 www.powerint.com bypass/multi-function pin undervoltage the bypass/multi-function pin undervoltage circuitry disables the power mosfet when the bypass/multi- function pin voltage drops below 4.9 v in steady state operation. once the bypass/multi-function pin voltage drops below 4.9 v in steady state operation, it must rise back to 5.85 v to enable (turn-on) the power mosfet. over temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is typically set at 142 c with 75 c hysteresis. when the die temperature rises above this threshold, the power mosfet is disabled and remains disabled, until the die temperature falls by 75 c, at which point it is re-enabled. a large hysteresis of 75 c (typical) is provided to prevent overheating of the pc board due to a continuous fault condition. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by typical capacitance and secondary-side rectifer reverse recovery time will not cause premature termination of the switching pulse. auto-restart in the event of a fault condition such as output overload, output short circuit, or an open loop condition, tinyswitch-pk enters into auto-restart operation. an internal counter clocked by the oscillator is reset every time the en/uv pin is pulled low. if the en/uv pin is not pulled low for 8192 switching cycles (or 32 ms), the power mosfet switching is normally disabled for 1 second (except in the case of line undervoltage condition, in which case it is disabled until the condition is removed). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. figure 5 illustrates auto-restart circuit operation in the presence of an output short circuit. in the event of a line undervoltage condition, the switching of the power mosfet is disabled beyond its normal 1 second until the line undervoltage condition ends. adaptive switching cycle on-time extension adaptive switching cycle on-time extension keeps the cycle on until current limit is reached, instead of prematurely terminating after the dc max signal goes low. this feature reduces the minimum input voltage required to maintain regulation, typically extending hold-up time and minimizing the size of bulk capacitor required. the on-time extension is disabled during the startup of the power supply, and after auto-restart, until the power supply output reaches regulation. line undervoltage sense circuit the dc line voltage can be monitored by connecting an external resistor from the dc line to the en/uv pin. during power-up or when the switching of the power mosfet is disabled in auto-restart, the current into the en/uv pin must exceed 25 m a to initiate switching of the power mosfet. during power-up, this is accomplished by holding the bypass/ multi-function pin to 4.9 v while the line undervoltage condition exists. after the line undervoltage condition goes away and the bypass/multi-function pin has stabilized at 5.85 v, switching is initiated. once mosfet switching is enabled, the dc line voltage is ignored unless the power supply enters auto-restart mode in the event of a fault condition. when the switching of the power mosfet is disabled in auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. this stretches the disable time beyond its normal 1 second until the line undervoltage condition ends. the line undervoltage circuit also detects when there is no external resistor connected to the en/uv pin (less than ~1 m a into the pin). in this case the line undervoltage function is disabled. tinyswitch-pk operation tinyswitch-pk devices operate in the current limit mode. when enabled, the oscillator turns the power mosfet on at the beginning of each cycle. the mosfet is turned off when the current ramps up to the current limit or when the dc max limit is reached (applicable when on-time extension is disabled). since the highest current limit level and frequency of a tinyswitch-pk design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. if the tinyswitch-pk is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the dc max limit is reached. pi-4320-030106 0 1000 2000 ti me (ms) 0 5 0 10 100 200 300 v drain v dc-output figure 5. auto-restart operation.
rev. c 09/12 5 tny375-380 www.powerint.com enable function tinyswitch-pk senses the en/uv pin to determine whether or not to proceed with the next switching cycle. the sequence of cycles is used to determine the current limit. once a cycle is started, it always completes the cycle (even when the en/uv pin changes state halfway through the cycle). this operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle, and the delay of the feedback. the en/uv pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. the en/uv pin signal is high when the power supply output voltage is less than the reference voltage. in a typical implementation, the en/uv pin is driven by an optocoupler. the collector of the optocoupler transistor is connected to the en/uv pin, and the emitter is connected to the source pin. the optocoupler led is connected in series with a zener diode across the dc output voltage to be regulated. when the output voltage exceeds the target regulation voltage level (optocoupler led voltage drop plus zener voltage), the optocoupler led will start to conduct, pulling the en/uv pin low. the zener diode can be replaced by a tl431 reference circuit for improved accuracy. on/off operation with current limit state machine the internal clock of the tinyswitch-pk runs at all times. at the beginning of each clock cycle, it samples the en/uv pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. at high loads, the state machine sets the current limit to its highest value. with tinyswitch-pk, when the state machine sets the current limit to its highest value, the oscillator frequency is also doubled, providing the unique peak mode operation. at lighter loads, the state machine sets the current limit to reduced values. at these lower current limit levels, the oscillator frequency returns to the standard value. at near maximum load, tinyswitch-pk will conduct during nearly all of its clock cycles (figure 6). at slightly lower load, it will skip additional cycles in order to maintain voltage regulation at the power supply output (figure 7). at medium loads, more cycles will be skipped, the current limit will be v drain v en clock dc drain i max pi-2749-082305 v drain v en clock dc drain i max pi-2667-082305 figure 6. operation at near maximum loading (f osc 264 khz). figure 7. operation at moderately heavy loading (f osc 264 khz). pi-4540-050407 v drain v en clock dc drain i max figure 8. operation at medium loading (f osc 132 khz).
rev. c 09/12 6 tny375-380 www.powerint.com pi-4541-042507 v drain v en clock d drain i max figure 9. operation at very light load (f osc 132 khz). 0 1 2 t ime (ms) 0 200 400 5 0 10 0 100 200 pi-4865-101007 v dc-input v byp ass v drain pi-4866-101007 0 1 2 t ime (ms) 0 200 400 5 0 10 0 100 200 v dc-input v byp ass v drain pi-2348-030801 0 .5 1 ti me (s) 0 100 200 300 0 100 200 400 v dc-input v drain pi-2395-030801 0 2.5 5 ti me (s) 0 100 200 400 300 0 100 200 v dc-input v drain figure 10. power-up with optional external uv resistor (4 m w) connected to en/uv pin. figure 11. power-up without optional external uv resistor connected to en/uv pin. figure 12. normal power-down timing (without uv resistor). figure 13. slow power-down timing with optional external (4 m w) uv resistor connected to en/uv pin.
rev. c 09/12 7 tny375-380 www.powerint.com reduced, and the clock frequency is reduced to half that at the highest current limit level (figure 8). at very light loads, the current limit will be reduced even further (figure 9). only a small percentage of cycles will occur to satisfy the power consumption of the power supply. the response time of the on/off control scheme is very fast compared to pwm control. this provides tight regulation and excellent transient response. power up/down the tinyswitch-pk requires only a 0.1 m f capacitor on the bypass/multi-function pin to operate with standard current limit. because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. the time to charge will vary in proportion to the bypass/multi- function pin capacitor value when selecting different current limits. due to the high bandwidth of the on/off feedback, there is no overshoot at the power supply output. when an external resistor (4 m w ) is connected from the power supply positive dc input to the en/uv pin, the power mosfet switching will be delayed during power-up until the dc line voltage exceeds the threshold (100 v). figures 10 and 11 show the power-up timing waveform in applications with and without an external resistor (4 m w ) connected to the en/uv pin. during power-down, when an external resistor is used, the power mosfet will switch for 32 ms after the output loses regulation. the power mosfet will then remain off without any glitches since the undervoltage function prohibits restart when the line voltage is low. figure 12 illustrates a typical power-down timing waveform. figure 13 illustrates a very slow power-down timing waveform, as in standby applications. the external resistor (4 m w ) is connected to the en/uv pin in this case to prevent unwanted restarts. with the tny375 and tny376, no bias winding is needed to provide power to the chip because it draws the power directly from the drain pin (see functional description above). this eliminates the cost of a bias winding and associated components. for the tny377-380 or for applications that require very low no-load power consumption (50 mw), a resistor from a bias winding to the bypass/multi-function pin can provide the power to the chip. the minimum recommended current supplied is i s2 + i dis . the bypass/multi-function pin in this case will be clamped at 6.4 v. this method will eliminate the power draw from the drain pin, thereby reducing the no-load power consumption and improving full-load effciency. current limit operation each switching cycle is terminated when the drain current reaches the current limit of the device. current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage. bypass/multi-function pin capacitor the bypass/multi-function pin can use a ceramic capacitor as small as 0.1 m f for decoupling the internal power supply of the device. a larger capacitor size can be used to adjust the current limit. a 1 m f bp/m pin capacitor will select a lower current limit equal to the standard current limit of the next smaller device, and a 10 m f bp/m pin capacitor will select a higher current limit equal to the standard current limit of the next larger device. the tny375 and tny376 mosfets do not have the capability to match the current limit of the next larger devices in the family. the current limit is therefore increased to the maximum capability of their respective mosfets. the higher current limit level of the tny380 is set to 1105 ma typical. the smaller current limit of the tny375 is set to 325 ma.
rev. c 09/12 8 tny375-380 www.powerint.com applications examples the circuit shown in figure 14 is a low cost universal ac input, four-output fyback power supply utilizing a tny376. the continuous output power is 7.5 w with a peak of 13 w. the output voltages are 3.3 v, 5 v, 12 v, and C12 v. the rectifed and fltered input voltage is applied to the primary winding of t1. the other side of the transformers primary is driven by the integrated mosfet in u1. diode d5, c3, r1, r2, and vr1 compose the clamp circuit, limiting the leakage inductance turn-off voltage spike on the drain pin to a safe value. the use of a combination zener clamp and parallel rc optimizes both emi and energy effciency. both the 3.3 v and 5 v outputs are sensed through resistors r6 and r7. the voltage across r8 is regulated to 2.5 v by reference ic u3. if the voltage across r8 begins to exceed 2.5 v, then current will fow in the led inside the optocoupler u2, driven by the cathode of u3. this will cause the transistor of the optocoupler to sink current from the en/uv pin of u1. when the current exceeds the enable pin threshold current, the next switching cycle is inhibited. conversely, when the voltage across resistor r8 falls below 2.5 v, and the current out of the enable pin is below the threshold, a conduction cycle is allowed to occur. by adjusting the number of enabled cycles, regulation is maintained. as the load reduces, the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. this provides almost constant effciency down to very light loads, ideal for meeting energy effciency requirements. the input flter circuit (c1, l1 and c2) reduces conducted emi. to improve common mode emi, this design makes use of e-shield tm shielding techniques in the transformer, reducing common mode displacement currents, and reducing emi. these techniques, combined with the frequency jitter of tny376, give excellent emi performance, with this design achieving >10 db m v of margin to en55022 class b conducted emi limits. for design fexibility, the value of c4 can be selected to pick one of the three current limit options in u4. doing so allows the designer to select the current limit appropriate for the application. ? standard current limit is selected with a 0.1 mf bp/m pin capacitor and is the normal choice for typical applications. ? when a 1 m f bp/m pin capacitor is used, the current limit is reduced, offering reduced rms device currents and therefore improved effciency, but at the expense of maximum power capability. this is ideal for thermally challenging designs where dissipation must be minimized. ? when a 10 m f bp/m pin capacitor is used, the current limit is increased, extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. further fexibility comes from the current limits between adjacent tinyswitch-pk family members being compatible. the reduced current limit of a given device is equal to the standard current limit of the next smaller device, and the increased current limit is equal to the standard current limit of the next larger device. figure 14. tny376pn, four output, 7.5 w, 13 w peak universal input power supply. d9 uf4003 u1 tny376p u2a ltv817a u3 l431 2% c1 22 f 400 v c2 22 f 400 v c3 10 nf 1 kv c4 10 f 50 v c11 47 f 25 v c14 100 nf 50 v c13 10 f 50 v c9 1000 f 10 v c5 220 f 25 v c10 470 f 10 v c8 470 f 10 v c6 100 f 25 v c7 1000 f 25 v c12 220 f 25 v u2b ltv817a jp1 jp2 c5 330 pf 250 vac r1 100 ? r4 200 ? 1/2 w r6 20 k? 1% r5 1 k? r7 6.34 k? 1% r8 10 k? 1% r9 3.3 k? r2 47 ? r3 1 ? 1/2 w l1 5 mh l2 3.3 h l3 3.3 h l4 3.3 h f1 3.15 a 85-265 vac +12 v, 0.25 a +5.0 v, 0.5 a +3.3 v, 0.5 a rtn -12 v, 0.03 a l n d1 fr106 d2 fr106 d5 fr106 d6 uf4003 d7 1n5819 d8 sb340 vr1 p6ke180a d3 1n4007 d4 1n4007 pi-4673-012009 t1 eel19 1 n.c. 6 11 7 8,9,10 12 4 3 5 d s en/uv bp tinyswitch-pk
rev. c 09/12 9 tny375-380 www.powerint.com key application considerations tinyswitch-pk design considerations output power table data sheet maximum output power table (table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. the minimum dc input voltage is 100 v or higher for 85 vac input, or 220 v or higher for 230 vac input or 115 vac with a voltage doubler. the value of the input capacitance should be sized to meet these criteria for ac input designs. 2. effciency of 75%. 3. minimum data sheet value of i 2 f. 4. transformer primary inductance tolerance of 10%. 5. refected output voltage (v or ) of 135 v. 6. voltage only output of 12 v with an ultrafast pn rectifer diode. 7. continuous conduction mode operation with transient k p * value of 0.25. 8. increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 9. the part is board mounted with source pins soldered to suffcient area of copper and/or a heat sink is used to keep the source pin temperature at or below 110 c for p and g package and 100 c for d packaged devices. 10. ambient temperature of 50 c for open frame designs and 40 c for sealed adapters. *k p . below a value of 1, k p is the ratio of ripple to peak primary current. a transient k p limit of 0.25 is recommended to avoid premature termination of switching cycles due to initial current limit (i init ) being exceeded, which reduces maximum output power capability. the values shown in table 1 for peak power assume operation in i limitpeakinc . for reference, table 2 provides peak output powers for each family member at all three selectable current limit modes. for both table 1 and table 2, the peak output power values are limited electronically, based on minimum device i 2 f. stated differently, with suffcient heat sinking, these values could be delivered indefnitely, but in most cases this would be impractical. adapter and open frame power values are thermally limited and represent the practical continuous (or average) output power in two common thermal environments. over voltage protection the output overvoltage protection provided by tinyswitch-pk uses an internal latch that is triggered by a threshold current of approximately 7 ma into the bypass pin. in addition to an internal flter, the bypass pin capacitor forms an external flter, providing noise immunity from inadvertent triggering. for the bypass capacitor to be effective as a high frequency flter, it peak output power table product 230 vac 15% 85-265 vac i limit- peakred i limitpeak i limit- peakinc i limit- peakred i limitpeak i limit- peakinc TNY375P/g/d 8.5 w 14.5 w 16.5 w 5.5 w 11.5 w 12.5 w tny376p/g/d 10 w 19 w 22 w 6 w 15 w 17 w tny377p/g 13 w 23 w 28 w 8 w 18 w 23 w tny378p/g 16 w 27.5 w 34 w 10 w 21.5 w 27 w tny379p/g 18 w 31.5 w 39 w 12 w 25 w 31 w tny380p/g 20 w 36 w 45 w 14 w 28 w 35 w table 2. peak output power capability vs current limit mode selection. u1 tny380p c1 10 f 400 v c2 22 f 400 v l1 1 mh r1 1 k? r9 3.9 m? r5 47 ? 1/8 w r3 2 k? 1/8 w r4 20 ? r2 390 ? 1/8 w r6 21 k? 1% r10 3.9 m? c8 10 nf 1 kv c7 1 f 50 v c3 1000 f 16 v c4 1000 f 16 v c5 220 f 16 v c6 10 f 50 v u2 pc817a vr2 1n5251b, 22 v vr1 bzx55b11 11 v, 2% c9 2.2 nf 250 vac r7 22 ? 1/2 w f1 3.15 a 185 - 265 vac +12 v rtn l n d1 1n4007 d2 1n4007 d7 uf4007 d5 sb560 vr3 p6ke170a d6 uf4004 d3 1n4007 d4 1n4007 pi-4674-012009 t1 efd25 9,10 1 3 6,7,8 5 2 d s en/uv bp tinyswitch-pk l2 3.3 h figure 15. single 230 vac input 20 w continuous and 45 w peak power supply using tny380pn.
rev. c 09/12 10 tny375-380 www.powerint.com should be located as close as possible to the source and bypass pins of the device. for best performance of the ovp function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 v-30 v. this minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the ic device consumption. selecting the zener diode voltage to be approximately 6 v above the bias winding voltage (28 v for 22 v bias winding) gives good ovp performance for most designs but can be adjusted to compensate for variations in leakage inductance. adding additional fltering can be achieved by inserting a low value (10 w to 47 w ) resistor in series with the bias winding diode and/or the ovp zener, as shown by r4 and r5 in figure 15. the resistor in series with the ovp zener also limits the maximum current into the bypass pin. reducing no-load consumption with the exception of the tny375 and tny376, a bias winding must be used to provide supply current for the ic. this has the additional beneft of reducing the typical no-load consumption to <60 mw. select the value of the resistor (r6 in figure 15) to provide the data sheet supply current equal to i s2 + |i dis |. although in practice the bias voltage falls at low load, the reduction in supply current through r6 is balanced against the reduced ic consumption as the effective switching frequency reduces with load. audible noise the cycle skipping mode of operation used in the tinyswitch-pk devices can generate audio frequency components in the transformer. to limit this audible noise generation, the transformer should be designed such that the peak core fux density is below 3000 gauss (300 mt). following this guideline, and using the standard transformer production technique of dip varnishing practically eliminates audible noise. vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that results. ceramic capacitors that use dielectrics such as z5u, when used in clamp circuits, may also generate audio noise. if this is the case, try replacing them with a capacitor having a different dielectric or construction such as the flm foil or metallized foil type. tinyswitch-pk layout considerations single point grounding use a single point ground connection from the input flter capacitor to the area of copper connected to the source pins. when used as an auxiliary supply in a larger converter, a local dc bus decoupling capacitor is recommended. a value of 100 nf is typical. the bias winding should be returned directly to the input or decoupling capacitor. this routes surge currents away from the device during common mode line surge events. bypass capacitor (c bp ) the bypass pin capacitor should be located as near as possible to the bypass and source pins using a kelvin connection. no power current should fow through traces connected to the bypass pin capacitor or optocoupler. if using smd components, a capacitor can be placed underneath the package directly between bp and source pins. when using a capacitor value of 1 m f or 10 m f to select the reduced or increased current limit mode, it is recommended that an additional 0.1 m f ceramic capacitor is placed directly between bp and source pins. enable/undervoltage pin node connections the en/uv pin is a low-current, low-voltage pin, and noise coupling can cause poor regulation and/or inaccurate line uv levels. traces connected to the en/uv pin must be routed away from any high current or high-voltage switching nodes, including the drain pin and clamp components. this also applies to the placement of the line undervoltage sense resistor (r uv ). drain connected traces must not be routed underneath this component. tinyswitch-pk determines the presence of the uv resistor via a ~1 m a current into the en/uv pin at startup. when the under- voltage feature is not used ensure that leakage current into the en/uv pin is <<1 m a. this prevents false detection of the presence of a uv resistor which may prevent correct start-up. as the use of no-clean fux may increase leakage currents (by reducing surface resistivity) care should be taken to follow the fux suppliers guidance, specifcally avoiding fux contamination. placing a 100 k w , 5% resistor between bp and en/uv pins eliminates this requirement by feeding current >i luv(max) into the en/uv pin. primary loop area the area of the primary loop that connects the input flter capacitor, transformer primary, and tinyswitch-pk device should be kept as small as possible. primary clamp circuit a clamp is used to limit peak voltage on the drain pin at turn off. this can be achieved by using an rcd clamp or a zener and diode clamp across the primary winding. in all cases, to minimize emi, care should be taken to minimize the loop length from the clamp components to the transformer and the tinyswitch-pk device. thermal considerations the four source pins are internally connected to the ic lead frame and provide the main path to remove heat from the device. therefore all the source pins should be connected to a copper area underneath the tinyswitch-pk integrated circuit to act not only as a single point ground, but also as a heat sink. as this area is connected to the quiet source node, it should be maximized for good heat sinking. similarly, for axial output diodes, maximize the pcb area connected to the cathode.
rev. c 09/12 11 tny375-380 www.powerint.com y-capacitor the placement of the y-capacitor should be directly from the primary input flter capacitor positive terminal to the common/ return terminal of the transformer secondary. such a placement will route high magnitude common mode surge currents away from the tinyswitch-pk device. note C if an input (c, l, c) emi flter is used, then the inductor in the flter should be placed between the negative terminals on the input flter capacitors. optocoupler place the optocoupler physically close to the tinyswitch-pk device to minimize the primary side trace lengths. keep the high current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. output diode for best performance, the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor should be minimized. in addition, for axial diodes, suffcient copper area should be provided at the anode and cathode terminal of diode for heat sinking. a larger area is preferred at the quiet cathode terminal. a large anode area can increase high frequency radiated emi. quick design checklist as with any power supply design, all tinyswitch-pk designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify the v ds does not exceed 650 v at highest input voltage and peak (overload) output power. the 50 v margin to the 700 v bv dss specifcation gives margin for design variation. 2. maximum drain current C at maximum ambient temperature, maximum input voltage, and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at startup. repeat under steady state conditions and verify that the leading edge current spike event is below i init at the end of the t leb(min) . under all conditions the maximum drain current should be below the specifed absolute maximum ratings. 3. thermal check C at specifed maximum output power, minimum input voltage, and maximum ambient temperature, verify that the temperature specifcations are not exceeded for tinyswitch-pk device, transformer, output diode, and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of tinyswitch-pk device as specifed in the data sheet. under low-line maximum power, a maximum tinyswitch-pk device source pin temperature of 110 c is recommended to allow for these variations. design tools up-to-date information on design tools can be found at the power integrations web site: www.powerint.com. figure 16. layout considerations for tinyswitch-pk using p package. top view pi-4675-090712 opto- coupler + - high-v oltage + - dc out input filter capacitor output rectier safety spacing t r a n s f o r m e r pri sec bias bias r uv bypass capacitor connection to device should be short route connections to en/uv pin (including undervoltage r esistor) away fr om drain connected traces copper ar ea for heat sinking retur n bias winding dir ectly to input capacitor maximize hatched copper ar eas ( ) for optimum heat sinking bp/m en/uv y1- capacitor s s s s pri c bp d tinyswitch-pk
rev. c 09/12 12 tny375-380 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 17 (unless otherwise specifed) min typ max units control functions output frequency see note a f osc state machine at highest current limit level t j = 25 c average 248 264 280 khz pk-pk jitter 16 f osc -low all lower current limit levels t j = 25 c average 132 pk-pk jitter 8 maximum duty cycle dc max s1 open 62 65 % en/uv pin upper turnoff threshold current i dis -150 -115 -90 ma en/uv pin voltage v en i en/uv = 25 ma 1.8 2.2 2.6 v i en/uv = -25 ma 0.8 1.2 1.6 drain supply current i s1 en/uv current > i dis (mosfet not switching) see note b 290 ma i s2 en/uv open (mosfet switching at f osc ) see note c tny375 385 520 ma tny376 460 600 tny377 570 710 tny378 740 900 tny379 870 1060 tny380 1100 1350 absolute maximum ratings (1,4) drain voltage ....................................................-0.3 v to 700 v drain peak current: tny375 ...................................... 0.6 a (5) tny376 ...................................... 0.8 a (5) tny377 ...................................... 1.4 a (5) tny378 ....................................... 2.2 a 5) tny379 ...................................... 2.9 a (5) tny380 ...................................... 4.3 a (5) en/uv voltage ....................................................... -0.3 v to 9 v en/uv current ........................................................... ... 100 ma bp/m voltage .................................................. ...... -0.3 v to 9 v storage temperature ...................................... -65 c to 150 c operating junction temperature (2) ................... -40 c to 150 c lead temperature (3) ........................................................ 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. maximum ratings specifed may be applied one at a time without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. 5. the peak drain current is allowed while the drain voltage is simultaneously less than 400 v. thermal impedance thermal impedance: p or g package: (q ja ) ............................ .... 70 c/w (2) ; 60 c/w (3) (q jc ) (1) ............................................... .. 11 c/w d package: (q ja ) ............................ .. 100 c/w (2) ; 80 c/w (3) (q jc ) (2) ............................ ..................... 30 c/w notes: 1. measured on the source pin close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad.
rev. c 09/12 13 tny375-380 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 17 (unless otherwise specifed) min typ max units control functions (cont.) bp/m pin charge current i ch1 v bp/m = 0 v, t j = 25 c see note d, e tny375-378 -8.3 -5.4 -2.5 ma tny379-380 -9.7 -7.1 -3.9 i ch2 v bp/m = 4 v, t j = 25 c see note d, e tny375-378 -5 -3.5 -1.5 tny379-380 -6.6 -4.8 -2.1 bp/m pin voltage v bp/m see note d 5.6 5.85 6.15 v bp/m pin voltage hysteresis v bp/mh 0.80 0.95 1.20 v bp/m pin shunt voltage v shunt i bp = 2 ma 6.0 6.4 6.7 v en/uv pin line under- voltage threshold i luv t j = 25 c 22.5 25 27.5 ma circuit protection peak current limit (bp/m capacitor = 0.1 mf) see note e i limitpeak di/dt = 72 ma/ms t j = 25 c see note f TNY375P 330 355 380 ma tny375g/d 330 355 387 di/dt = 91 ma/ms t j = 25 c see note f tny376p 423 455 487 tny376g/d 423 455 496 di/dt = 117 ma/ms t j = 25 c see note f tny377p 544 585 626 tny377g 544 585 638 di/dt = 143 ma/ms t j = 25 c see note f tny378p 665 715 765 tny378g 665 715 779 di/dt = 169 ma/ms t j = 25 c see note f tny379p 786 845 904 tny379g 786 845 921 di/dt = 195 ma/ms t j = 25 c see note f tny380p 907 975 1043 tny380g 907 975 1063 peak current limit (bp/m capacitor = 1 mf) see note e i limitpeakred di/dt = 72 ma/ms t j = 25 c see note f TNY375P 302 325 361 ma tny375g/d 302 325 367 di/dt = 91 ma/ms t j = 25 c see note f tny376p 330 355 391 tny376g/d 330 355 401 di/dt = 117 ma/ms t j = 25 c see note f tny377p 423 455 501 tny377g 423 455 514 di/dt = 143 ma/ms t j = 25 c see note f tny378p 544 585 644 tny378g 544 585 661 di/dt = 169 ma/ms t j = 25 c see note f tny379p 665 715 787 tny379g tny380gn 665 715 808 di/dt = 195 ma/ms t j = 25 c see note f tny380p tny380g 786 845 930 786 845 955
rev. c 09/12 14 tny375-380 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 17 (unless otherwise specifed) min typ max units circuit protection (cont.) peak current limit (bp/m capacitor = 10 mf) see note e i limitpeakinc di/dt = 72 ma/ms t j = 25 c see note f TNY375P 349 375 413 ma tny375g/d 349 375 424 di/dt = 91 ma/ms t j = 25 c see note f tny376p 465 500 550 tny376g/d 465 500 565 di/dt = 117 ma/ms t j = 25 c see note f tny377p 665 715 787 tny377g 665 715 808 di/dt = 143 ma/ms t j = 25 c see note f tny378p 786 845 930 tny378g 786 845 955 di/dt = 169 ma/ms t j = 25 c see note f tny379p 907 975 1073 tny379g 907 975 1102 di/dt = 195 ma/ms t j = 25 c see note f tny380p 1028 1105 1216 tny380g 1028 1105 1249 power coeffcient i 2 f i 2 f = i limitpeak(typ) 2 f osc(typ) t j = 25 c bp/m capacitor = 0.1 mf tny375-380p 0.9 i 2 f i 2 f 1.12 i 2 f a 2 hz tny375-376d 0.9 i 2 f i 2 f 1.16 i 2 f tny375-380g 0.9 i 2 f i 2 f 1.16 i 2 f i 2 f = i limitpeakred(typ) 2 f osc(typ) t j = 25 c bp/m capacitor = 1 mf tny375-380p 0.9 i 2 f i 2 f 1.16 i 2 f tny375-376d 0.9 i 2 f i 2 f 1.20 i 2 f tny375-380g 0.9 i 2 f i 2 f 1.20 i 2 f i 2 f = i limitpeakinc(typ) 2 f osc(typ) t j = 25 c bp/m capacitor = 10 mf tny375-380p 0.9 i 2 f i 2 f 1.16 i 2 f tny375-376d 0.9 i 2 f i 2 f 1.20 i 2 f tny375-380g 0.9 i 2 f i 2 f 1.20 i 2 f initial current limit i init see figure 20 t j = 25 c, see note g 0.75 i limit(min) ma leading edge blanking time t leb t j = 25 c see note g tny375-377 190 235 ns tny378-380 145 190 current limit delay t ild t j = 25 c see note g, h 200 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sdh 75 c bp/m pin shutdown threshold current i sd 4 7 9 ma bp/m pin power-up reset threshold voltage v bp/m(reset) 1.6 2.6 3.6 v
rev. c 09/12 15 tny375-380 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 17 (unless otherwise specifed) min typ max units output on-state resistance r ds(on) tny375 i d = 28 ma t j = 25 c 19 22 w t j = 100 c 29 33 tny376 i d = 35 ma t j = 25 c 14 16 t j = 100 c 21 24 tny377 i d = 45 ma t j = 25 c 7.8 9.0 t j = 100 c 11.7 13.5 tny378 i d = 55 ma t j = 25 c 5.2 6.0 t j = 100 c 7.8 9.0 tny379 i d = 65 ma t j = 25 c 3.9 4.5 t j = 100 c 5.8 6.7 tny380 i d = 75 ma t j = 25 c 2.6 3.0 t j = 100 c 3.9 4.5 off-state drain leakage current i dss1 v bp/m = 6.2 v v en/uv = 0 v v ds = 560 v t j = 125 c see note i tny375-376 50 ma tny377-378 100 tny379-380 200 i dss2 v bp/m = 6.2 v v en/uv = 0 v v ds = 375 v, t j = 50 c see note g, i 15 breakdown voltage bv dss v bp = 6.2 v, v en/uv = 0 v, see note j, t j = 25 c 700 v drain supply voltage 50 v auto-restart on-time at f osc t ar t j = 25 c see note k 32 ms auto-restart duty cycle dc ar t j = 25 c 3 %
rev. c 09/12 16 tny375-380 www.powerint.com notes: a. for all bp/m pin capacitor values. b. i s1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. total device consumption at no-load is the sum of i s1 and i dss2 . c. since the output mosfet is switching, it is diffcult to isolate the switching current from the supply current at the drain. an alternative is to measure the bp/m pin current at 6.1 v. d. bp/m pin is not intended for sourcing supply current to external circuitry. e. to ensure correct current limit, it is recommended that nominal 0.1 mf / 1 mf / 10 m f capacitors are used. in addition, the bp/m capacitor value tolerance should be equal to or better than indicated below across the ambient temperature range of the target application. the minimum and maximum capacitor values are guaranteed by characterization. f. for current limit at other di/dt values, refer to figure 24. measurements made with device self-biased. g. this parameter is derived from characterization. h. this parameter is derived from the change in current limit measured at 1x and 4x of the di/dt shown in the i limit specifcation. i. i dss1 is the worst-case off state leakage specifcation at 80% of bv dss and maximum operating junction temperature. i dss2 is a typical specifcation under worst-case application conditions (rectifed 265 vac) for no-load consumption calculations. j. breakdown voltage may be checked against minimum bv dss specifcation by ramping the drain pin voltage up to but not exceeding minimum bv dss . k. auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). nominal bp/m pin cap value tolerance relative to nominal capacitor value min max 0.1 mf -60% +100% 1 mf -50% +100% 10 mf -50% na
rev. c 09/12 17 tny375-380 www.powerint.com pi-4079-080905 0.1 f 10 v 50 v 470 5 w s2 470 note: this test cir cuit is not applicable for curr ent limit or output characteristic measur ements. sd en/uv s s bp/m s 150 v s1 2 m pi-2364-012699 en/uv t p t en/uv dc max t p = 1 f osc v drain (internal signal) 0.8 figure 17. general test circuit. figure 18. duty cycle measurement. figure 19. output enable timing. figure 20. current limit envelope at f osc = 132 khz.
rev. c 09/12 18 tny375-380 www.powerint.com 1.1 1.0 0.9 -50 -25 02 55 07 5 100 125 150 junction temperature (c) breakdown voltage (normalized to 25 c) pi-2213-012301 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction t emperature (c) pi-2680-012301 output frequency (normalized to 25 c) 1 0.8 0.6 0.4 0.2 0 -50 05 0 100 150 t emperature (c) pi-4102-010906 1.2 standard current limit (normalized to 25 c) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 normalized di/dt pi-4268-042707 normalized current limit tny375 72 ma/s tny376 91 ma/s tny377 117 ma/s tny378 143 ma/s tny379 169 ma/s tny380 195 ma/s normalized di/dt = 1 note: for the normalized current limit value, use the typical current limit specified for the appropriate bp/m capacitor. drain v oltage (v) drain current (ma) 450 375 300 150 75 225 0 02 46 81 0 t case =25 ? c t case =100 ? c pi-4267-120406 tny375 1.0 tny376 1.33 tny377 2.33 tny378 3.67 tny379 4.87 tny380 7.33 scaling factors: drain v oltage (v) drain capacitance (pf) pi-4269-120406 0 100 200 300 400 500 600 1 10 100 1000 tny375 1.0 tny376 1.33 tny377 2.33 tny378 3.67 tny379 4.87 tny380 7.33 scaling factors: figure 21. breakdown vs. temperature. figure 22. frequency vs. temperature. figure 23. standard current limit vs. temperature. figure 24. current limit vs. di/dt. figure 25. output characteristics. figure 26. c oss vs. drain voltage.
rev. c 09/12 19 tny375-380 www.powerint.com 150 90 120 30 60 0 0 200 400 600 drain v oltage (v) power (mw) pi-4270-120406 tny375 1.0 tny376 1.33 tny377 2.33 tny378 3.67 tny379 4.87 tny380 7.33 scaling factors: 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 02 55 07 5 100 125 junction temperature ( c) pi-2698-012301 under-voltage threshold (normalized to 25 c) figure 27. drain capacitance power. figure 28. undervoltage threshold vs. temperature.
rev. c 09/12 20 tny375-380 www.powerint.com notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body . 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08c pdip-8c (p package) pi-3933-040110 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum smd-8c (g package) pi-4015-101507 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 3 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measured at package body . 6. d and e are referenced datums on the package body . .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08c .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions .137 (3.48) minimum
rev. c 09/12 21 tny375-380 www.powerint.com pi-4526-0401 10 d07c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr . 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc sea ting plane 0.25 (0.010) 0.17 (0.007) det ail a det ail a c sea ting plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions + so-8c (d package) part ordering information ? tinyswitch product family ? series number ? package identifer g plastic surface mount smd-8c p plastic dip-8c d plastic surface mount so-8c ? lead finish n pure matte tin (pb-free) (not available in d package) g rohs compliant and halogen free (d package only) ? tape & reel and other options blank standard confguration tl tape & reel, 1000 pcs min./mult., g package, 2500 pcs min./mult., d package tny 278 g n - tl
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2012, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a release fnal data sheet. 05/07 b added g package and updated limits. 11/07 c updated part ordering information section with halogen free and added d package parts. 07/09 c updated figure 16 layout schematic. 09/12

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